Chapter 5: EDA Software & Semiconductor IP

5.1 Overview

Every chip begins as a design. Before a single transistor is fabricated, before a wafer enters a lithography tool, an engineer uses electronic design automation (EDA) software to create, simulate, verify, and prepare the chip’s blueprint for manufacturing. EDA is the invisible software layer that translates human intent into the precise geometric patterns that foundries etch into silicon. Semiconductor intellectual property (IP) consists of pre-designed, pre-verified functional blocks (processor cores, interface controllers, memory compilers) that chip designers license and integrate into their own chips, avoiding the need to design every component from scratch.

This chapter connects directly to Chapter 6 (Chip Design) above it, because every chip designer (NVIDIA, AMD, Apple, or a hyperscaler’s custom silicon team) depends on EDA tools and licensed IP. It connects to Chapter 7 (Foundries) through the “design-to-foundry handoff,” the process by which a completed chip design is certified for a specific manufacturing process node. EDA vendors and foundries co-develop process design kits (PDKs) that ensure the design will work when fabricated. Without this handoff, a chip design is just a file.

What makes this layer strategically important is extreme concentration and stickiness. Three companies (Synopsys, Cadence Design Systems, and Siemens EDA, formerly Mentor Graphics) collectively control approximately 75% of the global EDA market ¹²³. In semiconductor IP, Arm Holdings dominates processor architecture with over 99% of smartphone application processors ¹³¹⁴ and a growing share of data center chips using Arm-based designs. The EDA oligopoly is reinforced by deep foundry certification. A chip designer using Synopsys tools certified for TSMC’s N2P process cannot easily switch to Cadence without re-qualifying the entire design flow, a process that takes months and risks schedule delays.

The AI buildout amplifies demand for EDA in three ways. First, AI accelerators are among the most complex chips ever designed (NVIDIA’s Blackwell has over 200 billion transistors), requiring massive verification compute. Second, the explosion of custom AI silicon at hyperscalers (Google TPU, Amazon Trainium, Microsoft Maia, Meta MTIA) creates new design starts that each require EDA licenses and IP blocks. Third, the shift to chiplet-based multi-die architectures and 3D packaging (Chapter 9) requires new EDA capabilities for multi-die design, thermal simulation, and system-level verification. Synopsys’s acquisition of Ansys ($35 billion, completed July 2025) directly addresses this by combining chip-level EDA with system-level multiphysics simulation ⁴⁵.

5.2 Market Sizing & Growth

EDA software market: The global EDA market was valued at approximately $14.5-16.5 billion in 2025, depending on scope definition, and is projected to reach $20.8-30.7 billion by 2026-2031 at a CAGR of 8-9% ¹⁶⁷. The US market alone was approximately $16.5 billion in 2026 ⁸. Semiconductor IP (the fastest-growing sub-segment within EDA) is projected at a 9.7% CAGR through 2031 ⁶.

Semiconductor IP market: Valued at approximately $7.3-7.95 billion in 2025, projected to grow to $13.5 billion by 2030 at an 11.1% CAGR ⁹¹⁰. Arm Holdings dominates with roughly 41% market share in processor IP. Synopsys is the #2 semiconductor IP vendor by revenue (13% share), followed by Imagination Technologies (8%), Cadence (5%), and Fujitsu (4%) ¹¹.

Key company revenues:

Synopsys: FY2025 (Oct) revenue $7.054B (+15% YoY); Ansys contributed $756.6M. Q1 FY2026 revenue $2.41B (+66% YoY). FY2026 guidance narrowed to $9.56-9.66B (including ~$2.9B Ansys). $2B buyback authorized. ⁴⁵
Cadence: FY2025 (Dec) revenue $5.297B; backlog $7.8B. Q1 2026 revenue $1.474B (+18.7% YoY). FY2026 guidance raised to $6.125-6.225B. Record backlog $8.0B. Non-GAAP operating margin 44.7%. ¹²
Arm Holdings: FY2026 (Mar) revenue $4.92B (+23% YoY); Q4 FY2026 $1.49B (record). Royalty revenue $2.61B (+21%); licensing $2.31B (+25%). Data center royalty revenue more than doubled YoY. Long-term target >$9 EPS by FY2031 on $15B chip revenue. Market cap ~$227B. ¹³¹⁴

Cloud EDA: A growing sub-segment valued at approximately $4.15-4.18 billion in 2025-2026, projected at 6.7-8.1% CAGR depending on the source (Precedence Research at 6.74% ⁷, Mordor Intelligence at 8.11% ¹⁵). Cloud-based EDA is still early (approximately 69% of flows remain on-premise due to IP sensitivity), but adoption is accelerating as designs grow too complex for in-house compute clusters.

5.3 Supply Chain Flowchart

CHIP DESIGN REQUIREMENT
(from Chapter 6: NVIDIA, AMD, Apple, hyperscaler custom silicon teams, fabless startups)
    |
    v
SEMICONDUCTOR IP LICENSING
    |
    |---> PROCESSOR IP
    |    Arm Holdings: CPU cores (Cortex, Neoverse), GPU (Mali, Immortalis)
    |    RISC-V: Open-source ISA (SiFive, Andes, Tenstorrent designs)
    |    Synopsys: ARC processors, interface IP
    |    Imagination Technologies: GPU IP (PowerVR)
    |    CEVA: DSP and AI/ML IP
    |
    |---> INTERFACE IP
    |    Synopsys: PCIe, USB, DDR, Ethernet, UCIe, UALink
    |    Cadence: PCIe, DDR, die-to-die (D2D)
    |    Alphawave Semi: high-speed connectivity IP (SerDes, PCIe, UCIe)
    |    Rambus: memory interface, security IP
    |
    |---> MEMORY IP
    |    Synopsys: memory compilers, SRAM
    |    Arm: physical IP (standard cells, memory)
    |    eMemory Technology: NVM IP (OTP, MTP)
    |
    +---> FOUNDATION IP
         Arm: standard cell libraries, physical IP
         Synopsys: physical IP libraries
              |
              v
EDA DESIGN FLOW
    |
    |---> FRONT-END DESIGN (RTL → Logic)
    |    Synopsys: Design Compiler, Fusion Compiler
    |    Cadence: Genus, Innovus, Cerebrus (AI-driven)
    |    Siemens EDA: Catapult, Questa
    |
    |---> SIMULATION & VERIFICATION
    |    Synopsys: VCS, Verdi, ZeBu (emulation), HAPS (prototyping)
    |    Cadence: Xcelium, Palladium (emulation), Protium
    |    Siemens EDA: Questa, Veloce
    |    Synopsys.ai Copilot: AI-driven verification (40% turnaround reduction)
    |
    |---> PHYSICAL DESIGN & SIGNOFF
    |    Synopsys: IC Compiler II, PrimeTime, StarRC
    |    Cadence: Innovus, Tempus, Quantus
    |    Siemens EDA: Calibre (DRC/LVS, industry standard for signoff)
    |
    |---> MULTI-PHYSICS SIMULATION (new, post-Ansys acquisition)
    |    Synopsys/Ansys: thermal, structural, electromagnetic simulation
    |    Cadence: Celsius (thermal), Clarity (EM)
    |    Siemens EDA: Simcenter
    |
    +---> MANUFACTURING PREP & DFM
         Synopsys: IC Validator
         Cadence: Pegasus
         Siemens EDA: Calibre (dominant for DRC/LVS)
              |
              v
PROCESS DESIGN KIT (PDK) ←-- Co-developed by EDA vendor + FOUNDRY
    |  Synopsys certified for TSMC A16, N2P (Apr 2025)
    |  Cadence certified for TSMC, Samsung, Intel 18A
    |  Design rules, device models, standard cells
    |
    v
TAPEOUT → FOUNDRY (Chapter 7: TSMC, Samsung, Intel Foundry)
    |  Each tapeout at 3nm costs >$50M in mask and NRE costs
    |
    v
FABRICATION → PACKAGING (Chapters 07, 09) → TESTING (Chapter 4)

5.4 Key Companies

5.4.1 EDA Software Vendors

Company	Ticker	Exchange	Approx. Mkt Cap	Role	Key Metric
Synopsys	SNPS	NASDAQ	~$88.0B	Largest EDA company; ~31% global share; also #2 semiconductor IP vendor	FY2025 revenue $7.054B (+15%); completed $35B Ansys acquisition (Jul 2025); FY2026 guidance $9.61B; backlog $11.4B; ~5,000 active synopsys.ai users ⁴⁵
Cadence Design Systems	CDNS	NASDAQ	~$84.0B	#2 EDA company; ~30% global share; strong in custom/analog design	FY2025 revenue $5.297B; backlog $7.8B; Cerebrus AI-driven design tool; 40% YoY growth in system design and analysis ¹¹²
Siemens EDA (fmr. Mentor Graphics)	SIE (parent)	XETRA	~$130B (Siemens group)	#3 EDA; ~13% share; Calibre is industry standard for DRC/LVS signoff	Acquired by Siemens for $4.5B (2017); Calibre dominates manufacturing signoff; launched AI-enabled EDA suite and 3D IC tools (Jun 2025) ¹⁶
Ansys (now Synopsys sub.)	Private	(Acquired)	(Part of SNPS)	Multiphysics simulation: structural, thermal, electromagnetic, fluid	Acquired by Synopsys for $35B (completed Jul 2025); contributed $756.6M revenue in partial FY2025; expected $2.9B in FY2026 ⁴⁵
Keysight Technologies	KEYS	NYSE	~$62.0B	Test, measurement, and EDA tools for RF/microwave and signal integrity	PathWave design software; strong in 5G and high-frequency design
Altium	Private	Private (acquired by Renesas, A$9.1B, Aug 2024)	N/A	PCB design software; subsidiary of Renesas	Delisted from ASX Aug 2024. Dominant in PCB layout tools; growing in system-level integration
Silvaco	SVCO	NASDAQ	~$500M	TCAD simulation, EDA tools for specialty/analog processes	IPO’d May 2024 at $19/share. Niche but important for analog/mixed-signal and power device design

The Big Three EDA oligopoly (Synopsys, Cadence, Siemens EDA) is one of the most durable market structures in technology. Together they control roughly 75% of global EDA revenue ¹²³. The concentration is reinforced by several structural factors:

Foundry certification lock-in. A chip design must be certified for a specific foundry process (e.g., TSMC N2P). EDA vendors co-develop PDKs with foundries, and switching EDA vendor mid-design requires re-qualification, which is prohibitively expensive and time-consuming. Synopsys and TSMC certified full digital and analog toolchains for A16 and N2P in April 2025 ⁶.
Verification compute intensity. Verifying a modern AI chip (200B+ transistors) requires enormous compute resources. Hardware-assisted verification (emulation systems like Synopsys ZeBu and Cadence Palladium) costs $5-20M per system. This capital requirement raises barriers to entry.
IP integration. Synopsys and Cadence both sell IP blocks (interface, processor, memory) that are pre-verified with their own EDA tools. Using a competitor’s IP block in a Synopsys design flow creates friction. This vertical integration of EDA + IP creates a “walled garden” effect.
Tapeout cost escalation. A single tapeout at 3nm costs over $50M in mask and non-recurring engineering (NRE) costs ⁶. Designers cannot afford re-spins caused by tool errors, so they gravitate toward the most proven, foundry-certified tools.

Synopsys’s Ansys acquisition ($35B, completed July 2025) is the most significant EDA M&A event in years ⁴⁵¹⁶. It combines Synopsys’s chip-level EDA with Ansys’s system-level multiphysics simulation (thermal, structural, electromagnetic, fluid dynamics). The strategic logic: as chips become 3D-stacked multi-die systems (Chapter 9), designers need to simulate electrical behavior, thermal dissipation, mechanical stress, and signal integrity across the entire package. A designer using CoWoS with HBM needs to know if the package will overheat, whether thermal expansion will crack solder joints, and how electromagnetic interference between chiplets affects signal quality. Ansys provides those simulation tools. The combined entity guides FY2026 revenue at $9.61B with ~40.5% non-GAAP operating margin ⁵.

5.4.2 Semiconductor IP Providers

Company	Ticker	Exchange	Approx. Mkt Cap	Role	Key Metric
Arm Holdings	ARM	NASDAQ	~$227B	Dominant processor IP company; ~41% of semiconductor IP market	FY2026 revenue $4.92B (+23%); 96-97% gross margin; >99% of smartphone app processors use Arm; data center royalty more than doubled YoY ¹³¹⁴
Synopsys (IP segment)	SNPS	NASDAQ	~$88.0B	#2 semiconductor IP vendor; interface IP (PCIe, USB, DDR, UCIe, UALink), ARC processors	Design IP segment within Synopsys; provides reusable chip modules for data center connectivity and AI accelerators ⁴⁵
Cadence (IP business)	CDNS	NASDAQ	~$84.0B	Interface IP (PCIe, DDR), verification IP, Tensilica DSP cores	PCIe 5.0/6.0 and DDR5 IP for HPC/AI; strong in memory interface
Imagination Technologies	Private	Private	Private	GPU IP (PowerVR); acquired by Canyon Bridge (China-linked PE)	~8% semiconductor IP share; GPU IP licensed by Apple (historically), automotive, others
CEVA	CEVA	NASDAQ	~$1.0B	DSP and AI/ML IP for edge devices, 5G modems, IoT	Licensing + royalty model; acquired Intrinsix for chip design services
Alphawave Semi (acquired by Qualcomm, Dec 2025, ~$2.4B) ¹⁷	fmr. AWE	fmr. LSE	Acquired	High-speed connectivity IP (SerDes, PCIe 6.0, UCIe, CXL)	Now part of Qualcomm. Was critical for chiplet-to-chiplet links. Qualcomm exposure: QCOM (NASDAQ, ~$200B).
Rambus	RMBS	NASDAQ	~$14.0B	Memory interface IP, security IP, silicon IP	Memory interface controllers for DDR5, LPDDR5; data center security chips
eMemory Technology	3529	TWSE	~$3.0B	Non-volatile memory (NVM) IP: OTP, MTP, PUF	Dominant in embedded NVM IP; used in nearly every major foundry’s process
SiFive	Private	Private	Private	Leading RISC-V processor IP vendor	Backed by Intel Capital, Qualcomm, TSMC; P870 core targets data center
Andes Technology	6533	TWSE	~$1.0B	RISC-V processor IP; Taiwan-based	Growing RISC-V core portfolio; strong in embedded/IoT

Arm Holdings is to processor IP what ASML is to EUV lithography: the dominant, near-irreplaceable supplier. Arm does not manufacture chips; it designs processor architectures and licenses them to chip companies (Apple, Qualcomm, Samsung, MediaTek, NVIDIA, Amazon, Google) who build Arm-based processors. Arm’s business model generates revenue from both upfront license fees and per-chip royalties. The royalty model means Arm’s revenue grows with chip volumes and ASPs. For the AI buildout, Arm’s Neoverse platform (V-series for performance, N-series for efficiency) is gaining share in data center CPUs. Amazon’s Graviton (designed with Arm architecture and Synopsys EDA tools), NVIDIA’s Grace CPU, and Microsoft’s Cobalt all use Arm Neoverse cores ¹³¹⁴.

Arm’s 96-97% gross margin reflects the pure IP licensing model, but Arm faces a long-term structural threat from RISC-V, an open-source instruction set architecture. RISC-V eliminates license fees entirely, and adoption is growing rapidly (40% growth in RISC-V tool libraries from 2023-2024) ¹. SiFive, Andes Technology, and Tenstorrent are leading RISC-V design houses. China is particularly aggressive in RISC-V adoption as a way to reduce dependence on Arm (which is subject to US/UK export controls). However, Arm’s software ecosystem (decades of compiler optimization, operating system support, application compatibility) provides a moat that RISC-V has not yet replicated for high-performance computing workloads ¹⁴.

Alphawave Semi was acquired by Qualcomm in December 2025 for approximately $2.4 billion ¹⁷. It provided high-speed connectivity IP (SerDes, PCIe 6.0, UCIe, CXL) critical for chiplet-to-chiplet communication in multi-die packages. As the industry moves toward chiplet architectures (Chapters 6, 9), the physical layer IP that connects chiplets becomes a chokepoint. UCIe (Universal Chiplet Interconnect Express) is the emerging standard. Alphawave’s absorption into Qualcomm means this IP is now available only through Qualcomm licensing or through competitors (Synopsys, Cadence).

5.4.3 Chinese EDA Efforts

Company	Ticker	Exchange	Approx. Mkt Cap	Role	Key Metric
Empyrean Technology	301269	Shenzhen	~$5.0B	China’s largest domestic EDA company; ~6% of Chinese EDA market	Acquired Xpeedic (Mar 2025) for SiP and 3D IC capabilities; allocates ~80% of revenue to R&D ¹⁶
Primarius Technologies	688206	Shanghai SSE STAR	~$2.0B	Chinese EDA startup; backed by Huawei and state funds	Focused on analog/mixed-signal design tools

China’s domestic EDA companies remain far behind the Big Three. Synopsys, Cadence, and Siemens EDA together hold approximately 78-80% of China’s EDA market as of 2024 ¹. US export controls restrict the sale of advanced EDA tools to certain Chinese entities, but general commercial sales continue under license. China is investing heavily in domestic EDA through the National EDA Innovation Center in Nanjing and Made in China 2025 initiatives, but building a competitive full-flow EDA toolchain from scratch is a multi-decade challenge. The primary risk to Western EDA vendors is not Chinese competition but Chinese exclusion. If export controls expand to cover all EDA sales to China, it would cost Synopsys and Cadence a meaningful portion of revenue.

5.4.4 ASIC Design Services (Taiwan)

Company	Ticker	Exchange	Approx. Mkt Cap	Role	Key Metric
Alchip Technologies	3661	TWSE	~$8.0B	ASIC design services; bridge between hyperscaler designs and TSMC fabrication	One of three major TSMC design service partners. Revenue driven by AI ASIC tapeouts.
Global Unichip Corp (GUC)	3443	TWSE	~$6.0B	TSMC subsidiary providing ASIC design services	Primary design service arm of TSMC. Enables hyperscalers to tapeout custom chips on TSMC processes.
Faraday Technology	3035	TWSE	~$3.0B	ASIC design services; full-turnkey and IP	Third major Taiwanese design service house. Broader focus than Alchip/GUC.

ASIC design services are the bridge between a hyperscaler’s chip concept and a finished tapeout at TSMC. When Google designs a TPU or Amazon designs Trainium, they work with Broadcom or Marvell for the architecture (Chapter 6), but the physical design implementation, verification, and foundry handoff often involves one of these Taiwanese design service houses. Alchip, GUC (a TSMC subsidiary), and Faraday are the three dominant players. Their growing revenue reflects the explosion of custom AI silicon design starts. These companies are listed on TWSE and are under-covered by Western analysts despite sitting at a critical juncture in the custom ASIC pipeline.

5.5 Bottleneck Analysis

EDA tools (SEVERE, structural oligopoly): The Big Three’s 75% market share ¹²³, reinforced by foundry certification and tapeout cost escalation, makes EDA a severe structural bottleneck. Chip designers have no viable alternative for leading-edge design flows. A startup designing a 3nm AI chip must use Synopsys or Cadence tools certified for the target foundry process. The cost of switching is measured in months of delay and millions in re-verification compute. EDA spending is a small fraction of total chip development cost (typically 2-5%), making designers price-insensitive, the classic bottleneck characteristic described in Chapter 1, Section 1.8.

Arm processor IP (HIGH): Arm’s dominance in mobile is absolute (>99% of smartphone app processors) ¹³¹⁴. In data centers, Arm’s share is growing but not yet dominant, with x86 (Intel, AMD) still holding majority share. The AI buildout is actually loosening Arm’s bottleneck position slightly because NVIDIA, Google, and Amazon are designing custom CPUs where the choice between Arm and RISC-V is actively being evaluated. RISC-V provides a partial substitute for Arm in certain applications, reducing Arm’s bottleneck severity from “extreme” to “high.”

Interface IP (MODERATE-HIGH): High-speed interface IP (PCIe 6.0, DDR5, UCIe, CXL) is critical for AI chips that need massive memory bandwidth and chiplet-to-chiplet communication. Synopsys, Cadence, and Qualcomm (via its December 2025 acquisition of Alphawave Semi for ~$2.4B ¹⁷) are the primary providers. The complexity of designing and verifying a PCIe 6.0 PHY at 64 GT/s creates significant barriers to entry. The existence of three credible providers prevents monopoly pricing, but the consolidation (Alphawave into Qualcomm) narrows the field of independent IP vendors.

Hardware-assisted verification (MODERATE-HIGH): Emulation systems (Synopsys ZeBu, Cadence Palladium) and prototyping systems (Synopsys HAPS, Cadence Protium) are essential for verifying chips with 100B+ transistors. These are expensive ($5-20M per system), have long lead times, and only Synopsys and Cadence offer competitive products. As AI chip complexity grows (200B transistors for Blackwell, likely 500B by 2027), verification compute demand scales quadratically with transistor count, creating a potential capacity constraint.

Manufacturing signoff (Siemens Calibre dominance): Siemens EDA’s Calibre tool is the industry standard for design rule checking (DRC) and layout vs. schematic (LVS) verification. Nearly every major foundry requires Calibre signoff before accepting a tapeout. This gives Siemens a quiet but durable monopoly-like position in one critical step of the design flow, even though Synopsys (IC Validator) and Cadence (Pegasus) offer alternatives.

5.6 Risks

Export control risk: US EDA vendors (Synopsys, Cadence) face revenue risk if export controls on China expand. In May 2025, the Trump administration briefly paused EDA export licenses for China ⁵. A permanent expansion could cost billions in lost revenue and accelerate China’s domestic EDA development. Conversely, maintaining sales to China risks criticism from US policymakers concerned about enabling Chinese chip advancement.

AI-driven disruption of the EDA model: Synopsys’s Synopsys.ai Copilot and Cadence’s Cerebrus represent the beginning of AI-driven chip design automation. If AI tools reduce the number of engineer-hours needed per design, the total addressable market for EDA licenses could shrink even as chip complexity grows. This is a long-term risk (5-10 year horizon). In the near term, AI tools are additive (requiring additional compute and license seats) rather than substitutional.

RISC-V eroding Arm’s moat: If RISC-V achieves competitive performance in data center applications (which SiFive’s P870 core targets), Arm’s pricing power could compress. The AI buildout creates demand for custom cores optimized for specific inference workloads, where RISC-V’s design flexibility has advantages. However, Arm’s Neoverse ecosystem has years of head start in software optimization, and switching costs are high for hyperscalers with deployed Arm-based fleets.

Concentration risk: Both Synopsys and Cadence derive meaningful revenue from a small number of large semiconductor companies (TSMC, NVIDIA, Intel, Samsung, Qualcomm, Apple). If any of these customers brought EDA development in-house (which some have explored for narrow tool categories), it would reduce the TAM. NVIDIA, for example, has built internal EDA capabilities for certain verification tasks, though it still depends heavily on commercial tools.

Cyclicality (lower than other semiconductor segments): EDA revenue is largely subscription/license-based and tied to multi-year contracts. This creates more stable revenue streams than equipment or chip sales. Synopsys’s $11.4B backlog and Cadence’s $7.8B backlog provide 1-2 years of revenue visibility ⁴¹². However, a prolonged downturn in design starts (e.g., if hyperscaler capex collapses and custom chip programs are cancelled) would eventually reduce new license signings.

First principles check: Does the EDA oligopoly make sense? Yes. Building a competitive full-flow EDA toolchain requires decades of accumulated algorithms, process-specific models, and foundry relationships. A new entrant would need to replicate the software and the co-development history with every major foundry. The 2-4 year foundry certification process creates a natural barrier. The fact that China, despite massive state investment, has achieved only 6% domestic EDA market share after years of effort confirms the structural durability of this moat ¹.