Chapter 7
Foundries & Fabrication
Chapter 7: Foundries & Fabrication
7.1 Overview
Foundries turn chip designs into physical silicon. They are the manufacturing backbone of the semiconductor supply chain, consuming the equipment (Chapter 4), materials (Chapter 3), and EDA-certified designs (Chapter 5) described in earlier chapters, and feeding their output to the packaging houses (Chapter 9) and memory stacks (Chapter 8) that produce finished AI accelerators. Every wafer begins as a silicon ingot grown in a fused silica crucible made from high-purity quartz, 70-90% of which originates in a single district in Spruce Pine, North Carolina (see Chapter 2). The foundry layer’s apparent scale and sophistication rests, at its geological origin, on two mines.
The foundry market is the most concentrated layer in the buildout. TSMC holds approximately 67-70% of global foundry revenue and fabricates an estimated 92% of all AI chips at 7nm and below 123. Samsung Foundry is a distant second at roughly 7%, followed by SMIC (5.3%), UMC (4.4%), and GlobalFoundries (3.9%) 12. At the leading edge (3nm and below), TSMC’s dominance is even more extreme. No other foundry ships 3nm chips in meaningful volume. Samsung’s 3nm GAA process has struggled with yield, and Intel Foundry’s 18A node is still in pilot production.
This concentration creates the single largest geographic risk in the entire AI supply chain. TSMC’s advanced fabs are concentrated in Taiwan, with new fabs under construction in Arizona (US), Kumamoto (Japan via JASM joint venture), and Dresden (Germany via ESMC, a joint venture with Bosch, Infineon, and NXP). Intel’s planned Magdeburg, Germany fab was cancelled in mid-2025 (confirmed by CEO Lip-Bu Tan in July 2025). None of the diversification fabs will produce leading-edge volumes before 2027-2028. A disruption in Taiwan, from natural disaster, geopolitical conflict, or other causes, would halt the production of virtually every AI accelerator, high-end smartphone processor, and advanced networking chip on Earth.
7.2 Market Sizing & Growth
Global foundry market: Total foundry revenue reached approximately $41.7 billion in Q2 2025, implying an annual run rate of ~$165-170 billion 1. TSMC alone reported full-year 2025 revenue of $122.4 billion (NT$3.94 trillion) and Q1 2026 revenue of $35.9 billion (+40.6% YoY) 34. TSMC’s market cap is approximately $900 billion as of mid-2026.
Advanced node revenue concentration at TSMC: In Q1 2026, advanced technologies (7nm and below) accounted for 74% of TSMC’s wafer revenue, with 3nm at 25% and 5nm at 36% 4. Advanced nodes, once less than 10% of revenue, now represent nearly three-quarters of TSMC’s business 5.
Capacity data:
- TSMC 3nm: monthly capacity ~120-130K wafers at end of 2025, projected ~180K by end of 2026 (+40% YoY). Demand from NVIDIA, AMD, Intel, and automotive exceeds capacity 6.
- TSMC 2nm (N2): mass production began late 2025 with ~30-40K wafers/month; projected to ramp to ~100K by end of 2026. Each 2nm wafer priced at approximately $30,000, a 10-20% premium over 3nm (which averages $25,000-$27,000), below earlier speculation of a 50% increase 67.
- TSMC A16 (1.6nm): expected in H2 2026, incorporating backside power delivery 5.
TSMC capex: $40-42 billion in 2025, with 2026 guidance of $52-56 billion (70-80% directed to advanced processes, remainder to specialty and advanced packaging) 358. TSMC plans 3-5% price hikes for sub-5nm nodes in 2026 7.
7.3 Supply Chain Flowchart
CHIP DESIGNS (Chapter 6) SEMICONDUCTOR MATERIALS (Chapter 3)
| Tapeout-ready GDS files | Wafers, photoresists, gases, chemicals
| from NVIDIA, AMD, Apple, |
| Broadcom, hyperscalers |
v v
+----------------------------------------------------+
| FOUNDRIES |
| |
| LEADING EDGE (<=5nm) |
| |-- TSMC (67-70% share): 3nm, 2nm, A16 |
| |-- Samsung Foundry (7%): 3nm GAA, 2nm (planned) |
| +-- Intel Foundry (<1%): 18A (pilot) |
| |
| MATURE/SPECIALTY (>=7nm) |
| |-- TSMC: 7nm, 16nm, 28nm |
| |-- Samsung: 8nm, 14nm, 28nm |
| |-- SMIC (5.3%): 14nm+, 7nm (limited, no EUV) |
| |-- UMC (4.4%): 14nm, 22nm, 28nm |
| |-- GlobalFoundries (3.9%): 12nm, 22nm, 45nm |
| |-- HuaHong Group (2.6%): specialty, mature |
| +-- Tower Semiconductor (0.9%): analog, specialty |
| |
| EQUIPMENT CONSUMED (Chapter 4): |
| ASML (litho), AMAT/Lam/TEL (dep/etch), |
| KLA (inspection), Advantest (test) |
+----------------------------------------------------+
|
v
PROCESSED WAFERS → PACKAGING (Chapter 9: CoWoS, HBM stacking)
→ TEST (Chapter 4: Advantest, Teradyne)
→ SYSTEM INTEGRATION (Chapter 18)7.3.1 TSMC Global Fab Map (Selected)
TAIWAN (primary)
|-- Hsinchu: HQ, R&D, Fabs 2/3/5/6/8/12/14/15
|-- Taichung: Fabs 15B, AP5B (advanced packaging)
|-- Tainan: Fabs 18 (5nm/3nm), AP8 (packaging)
|-- Chiayi: New CoWoS facilities (2 fabs, mass production 2026-2027)
+-- Kaohsiung: 2nm fabs under construction
ARIZONA, USA
|-- Fab 21 Phase 1: 4nm, production started 2025
|-- Fab 21 Phase 2: 3nm, mass production H2 2027
+-- Fab 21 Phase 3: 2nm (announced)
JAPAN (Kumamoto)
|-- JASM Fab 1: 22nm/28nm, production started 2024
+-- JASM Fab 2: 6nm/12nm, then 3nm (2028)
GERMANY (Dresden)
+-- ESMC: 12nm/28nm (under construction, production 2027)7.4 Key Companies
| Company | Ticker | Exchange | Approx. Mkt Cap | Role | Key Metric |
|---|---|---|---|---|---|
| TSMC | 2330 / TSM | TWSE / NYSE | ~$2.2T | World’s largest foundry; 67-70% market share; sole volume producer of 3nm/2nm | FY2025 revenue $122.4B; Q1 2026 $35.9B (+40.6% YoY); advanced nodes 74% of revenue; 3nm capacity 180K/month by end 2026; 2nm at $30K/wafer 123467 |
| Samsung Foundry | 005930 | KRX | ~$1.2T (group) | #2 foundry (~7% share); 3nm GAA; HBM packaging in-house | Q2 2025 revenue $3.16B; 3nm GAA yields improving; quadrupling advanced packaging by 2028 12 |
| Intel Foundry | INTC | NASDAQ | ~$628B | US-based foundry; 18A process in pilot; CHIPS Act recipient | Received $8.5B CHIPS Act direct funding; 18A node with backside power delivery; first 18A products shipped (Jan 2026); revenue remains much smaller than TSMC 129 |
| SMIC | 981 / 688981 | HKEX / Shanghai SSE STAR | ~$50.0B | China’s largest foundry; 5.3% share; 14nm and above (no EUV access) | FY2025 revenue ~$9.3B (+16% YoY); adding more capacity than rest of world at mature nodes; limited by US export controls to DUV-based processes 1210 |
| UMC | 2303 / UMC | TWSE / NYSE | ~$18.0B | Taiwan-based; 4.4% share; mature/specialty nodes (14nm-28nm) | Q4 2025 revenue ~$2.0B; new Singapore fab (22nm/28nm, production 2026); stable utilization 12 |
| GlobalFoundries | GFS | NASDAQ | ~$40.6B | US-based (Malta, NY); 3.9% share; specialty (12nm, 22nm, 45nm) | Q4 2025 revenue $1.8B; strong in automotive, IoT, RF; no longer pursuing leading edge |
| Tower Semiconductor | TSEM | NASDAQ | ~$25.1B | Specialty foundry: analog, RF, power management, sensors | Israel-based; Intel attempted $5.4B acquisition (terminated 2023 due to regulatory issues); niche but important for automotive/industrial |
| HuaHong Group | 1347 | HKEX | ~$29.1B | Chinese specialty foundry; 2.6% share; mature nodes | Benefiting from China domestic substitution; expanding capacity |
| Vanguard International Semi (VIS) | 5347 | TWSE | ~$3.0B | TSMC subsidiary; mature/specialty nodes | 0.9% share; serves automotive and industrial |
| SkyWater Technology | SKYT | NASDAQ | ~$1.5B | US-only foundry; 90nm-130nm; CHIPS Act recipient | US government/defense focused; “trusted foundry” for DoD; received CHIPS Act funding |
TSMC’s dominance demands detailed analysis. In 2024, TSMC deployed 288 distinct process technologies and manufactured 11,878 different products for 522 customers 5. Its 2025 revenue of $122.4 billion represented 67-70% of all foundry revenue globally. Advanced technologies grew at 60%+ annually on average, while legacy nodes stagnated 5. TSMC’s pricing power is confirmed by its planned 3-5% price hikes on sub-5nm for 2026 7, and 2nm wafers priced at $30,000 each (50% above 3nm) 6. AI-related revenues are projected to double in 2025 and grow 40% annually for the next five years 5.
Samsung Foundry is TSMC’s only competitor at the leading edge. It was the first to commercialize gate-all-around (GAA) transistors at 3nm, but yield problems limited commercial adoption. Samsung is investing heavily: its Pyeongtaek P5 fab is resuming construction, and the company aims to quadruple advanced packaging output by 2028 8. Samsung’s “3.3D” advanced packaging technology for AI chips targets mass production in Q2 2026.
Intel Foundry represents the most ambitious turnaround in semiconductor history. Under the IDM 2.0 strategy, Intel is attempting to become a competitive foundry while simultaneously designing its own chips. The 18A node (with backside power delivery and GAA) shipped first products in January 2026 9. Intel received $8.5 billion in direct CHIPS Act funding plus $11 billion in loans. The strategic question is whether Intel can attract enough external customers to justify the massive investment. If successful, Intel Foundry would diversify the supply chain away from its Taiwan dependency. If it fails, it risks becoming a subsidized capacity that never reaches competitive yields.
SMIC is strategically important despite its technology limitations. Restricted from purchasing EUV lithography equipment by US export controls, SMIC is limited to DUV-based processes (14nm and above, with some 7nm using multi-patterning). It is adding more capacity at mature nodes than the rest of the world combined (see Chapter 1, Section 1.7). SMIC’s revenue grew 16% YoY to $9.3 billion in 2025 110. For the AI buildout thesis, SMIC’s importance is indirect: it supplies many of the peripheral chips (power management, sensor controllers, connectivity) that go into AI servers alongside the leading-edge accelerators.
7.5 Bottleneck Analysis
TSMC advanced node capacity (EXTREME): TSMC is the sole volume manufacturer of 3nm and 2nm chips. Every NVIDIA Blackwell GPU, every AMD MI350, every Apple A-series chip, every Google TPU, and every Amazon Trainium runs on TSMC silicon. CEO C.C. Wei confirmed the severity on TSMC’s Q3 2025 call: “All I want to say about the AI, everything related, like frontend and backend capacity is very tight” 13. The allocation of TSMC’s limited advanced node wafer starts is the most consequential resource allocation decision in the technology industry. A single quarter delay in TSMC capacity expansion delays the entire AI hardware supply chain.
Geographic concentration in Taiwan (EXTREME): TSMC’s advanced fabs are concentrated on a single island in a geopolitically sensitive region. On the Q1 2026 call, Wei confirmed TSMC is “executing a global capacity plan” with new fabs in Taiwan, Arizona, and Japan through 2028, but acknowledged capacity expansion requires 2-3 years per new fab with supply shortages expected through 2027 14. Diversification efforts are underway but years from leading-edge volumes: TSMC Arizona (4nm production started, 2nm planned), TSMC Kumamoto Japan (28nm/12nm operational), TSMC ESMC Germany (12nm/28nm, production 2027). Rapidus, Japan’s state-backed 2nm foundry effort, received $1.7B in funding (February 2026) 12 and is targeting pilot production 2025 with mass production in 2027 at its Chitose, Hokkaido IIM-1 facility; it collaborates with imec and IBM on process development but has not yet proven volume manufacturing capability. The US CHIPS Act ($52.7B, see Section 1.1) and allied subsidy programs aim to diversify, but new fab construction takes 3-5 years and yield ramp-up takes another 1-2 years. This risk is not hypothetical; it is the primary geopolitical risk factor for the global technology industry.
2nm pricing as an architecture and NRE filter (HIGH): At $30,000 per wafer 67, the per-wafer cost alone does not exclude smaller designs (a 5mm2 chip can yield 10,000+ dies per wafer, keeping unit cost at ~$3). The real barrier is the non-recurring engineering cost: a 2nm tapeout requires $40M+ for the mask set alone, plus hundreds of millions in EDA licensing, IP blocks, design verification, and multi-year development. Total NRE for a 2nm chip design exceeds $500M. This filters out all but the highest-volume, highest-ASP applications (AI accelerators, premium mobile SoCs, hyperscaler custom silicon), concentrating 2nm demand on a small number of design starts and creating a structural premium for TSMC.
Samsung Foundry yield (MODERATE): Samsung’s 3nm GAA yields have been reported as below expectations, limiting its ability to compete with TSMC for tier-1 customers like Qualcomm and NVIDIA. If Samsung’s yields improve, it provides a genuine alternative and reduces TSMC’s bottleneck. If yields remain problematic, TSMC’s monopoly at the leading edge persists.
7.6 Risks
Taiwan geopolitical risk: The most discussed risk in the semiconductor industry. A conflict or blockade affecting Taiwan would disrupt 67-70% of global foundry output 12 and more than 90% of leading-edge chip production 11. Mitigation (CHIPS Act, Arizona fabs) is underway but insufficient to eliminate the risk in the 2025-2028 timeframe. This risk is structural and cannot be diversified away within the current planning horizon.
Intel 18A success as a diversification catalyst: If Intel Foundry delivers competitive yields on 18A and attracts external customers (Qualcomm, NVIDIA, Broadcom), the foundry market diversifies materially. This is the bull case for Intel and the bear case for TSMC’s pricing power. Early signals are mixed: Intel shipped first 18A products but has not yet announced high-volume external customer commitments.
Overcapacity at mature nodes: China (SMIC, HuaHong) is adding massive capacity at 28nm and above, potentially creating a global glut of mature-node chips. This would compress margins for UMC, GlobalFoundries, and TSMC’s legacy business, but would not affect leading-edge pricing.
Capex cycle reversal: If the AI buildout slows (Chapter 1 bear case), foundry capex would decline sharply. TSMC’s $40-50B annual capex assumes continued AI demand growth. A reversal would create overcapacity and margin pressure, though TSMC’s dominant position means it would be the last foundry to feel the impact.
First principles check: Does TSMC’s dominance make sense? Yes. Leading-edge chip fabrication requires cumulative R&D investment measured in tens of billions, yield learning curves that take years to climb, and process-specific co-development with hundreds of customers. TSMC has been refining its foundry model for 38 years. Intel is attempting to replicate this in an accelerated timeframe; Samsung has been trying for over a decade. The concentration is structural, not accidental.