Chapter 9: Advanced Packaging & IC Substrates

9.1 Overview

Advanced packaging has become a critical bottleneck in the AI supply chain, and by some measures the binding constraint on near-term GPU output. The constraint on NVIDIA’s GPU output is not wafer fabrication (TSMC produces 3nm wafers in adequate volume) but the packaging step that bonds the GPU die to HBM memory on a single substrate. TSMC CEO C.C. Wei has stated publicly that CoWoS capacity is “very tight and remains sold out through 2025 and into 2026” ¹². NVIDIA reportedly secured over 60% of total CoWoS capacity for 2025-2026 ²³. The AI hardware bottleneck has moved from the transistor to the package. An analysis by Epoch AI quantifies this precisely: the four largest AI chip designers (NVIDIA, Google, AMD, Amazon) consumed approximately 90% of global CoWoS packaging capacity and HBM supply in 2025, while consuming only 12% of advanced logic die production ¹⁸. Logic die fabrication is NOT the binding constraint; packaging throughput is.

This chapter sits at the junction of several upstream layers. It consumes the equipment described in Chapter 4 (bonding tools from Besi, dicing from Disco, test equipment from Advantest), the materials from Chapter 3 (ABF film from Ajinomoto, silicon wafers for interposers), and serves the chip designers in Chapter 6, the foundries in Chapter 7, and the memory makers in Chapter 8. It is the bridge between a processed silicon die and a functional chip.

What is advanced packaging? Traditional packaging involves placing a single die on a substrate, connecting it with wire bonds, and encapsulating it. Advanced packaging integrates multiple dies (logic, memory, I/O) into a single package using techniques like 2.5D interposers (CoWoS), 3D stacking (SoIC, Foveros), fan-out wafer-level packaging (InFO), and hybrid bonding. The goal is to overcome the limits of monolithic chip scaling by combining smaller chiplets from different process nodes into a system that performs as if it were one large die.

Why it matters for the AI buildout: Every modern AI accelerator, whether NVIDIA’s Blackwell, AMD’s Instinct MI350, Google’s TPU, or Amazon’s Trainium, requires advanced packaging to achieve the memory bandwidth needed for AI workloads. The data transmission bandwidth between an AI chip packaged with CoWoS and HBM reaches the TB/s level, an order of magnitude higher than traditional packaging ⁴. Without advanced packaging, AI at scale does not work.

The ABF substrate dependency: Beneath every advanced package sits a substrate, almost always built using Ajinomoto Build-up Film (ABF). Five companies (Unimicron, Ibiden, AT&S, Nan Ya PCB, Shinko Electric) control approximately 74% of global ABF substrate production ⁵⁶. Intel, AMD, and NVIDIA have subsidized roughly 50% of the capital expansion projects of the four leading ABF suppliers because the supply is too critical and too concentrated to leave to market forces alone ⁷. ABF substrates are a small fraction of total chip cost but absolutely mission-critical, the same pricing power dynamic described in Chapter 3 for semiconductor materials.

9.2 Market Sizing & Growth

Advanced packaging market: According to Yole Group data, the global advanced packaging market surpassed 51% of the total semiconductor packaging market for the first time in 2025 and is projected to grow at a 10.6% CAGR to reach $78.6 billion by 2028 ⁴⁸. The market was valued at approximately $37.4 billion in 2021 and is forecast to reach $65 billion by 2027 ⁹. Advanced packaging’s share is projected to rise from roughly 40% in 2020 to over 60% by 2030 ⁹.

CoWoS specifically: Total global CoWoS demand is projected to grow from 370,000 wafer equivalents in 2024 to 670,000 in 2025 and 1 million in 2026 ⁴. TSMC is expanding CoWoS capacity aggressively, from roughly 35,000 wafers per month in early 2024 to a targeted 110,000-130,000 by late 2026 (a 3.1-3.7x increase over the period, though often described as “doubling annually” in industry shorthand) ²³. New facilities in Zhunan, Chiayi, Taichung, and Tainan are all contributing to this expansion. NVIDIA alone accounts for approximately 63% of total CoWoS demand ³.

ABF substrate market: Valued at approximately $4.9-5.3 billion in 2024-2025, projected to reach $9.5-10.4 billion by 2032-2033 at a CAGR of 10.4-10.7% ⁵⁶¹⁰. The 4-8 layer ABF segment holds 69% market share, while high-layer-count (16+) substrates for AI/HPC are growing fastest ⁵⁶. Morgan Stanley (April 2026) projects the server CPU ABF substrate market specifically at $4.7 billion by 2030, with agentic AI demand driving a 5-10% upward revision to substrate demand forecasts and a potential supply concern window in 2026-2027 ¹⁹.

OSAT (Outsourced Semiconductor Assembly & Test) market: The global OSAT market was approximately $43-45 billion in 2024, dominated by ASE Holdings, Amkor Technology, and JCET Group. Advanced packaging revenue at OSATs is growing much faster than legacy packaging: ASE expects advanced packaging revenue to grow from $600 million in 2024 to $1.6 billion in 2025 ¹¹.

Back-end equipment for packaging: As detailed in Chapter 4, packaging equipment sales were projected to reach $5-6 billion in 2025, with hybrid bonding equipment growing at a 21% CAGR (see Chapter 4, Section 4.4.7).

9.3 Supply Chain Flowcharts

9.3.1 CoWoS (Chip-on-Wafer-on-Substrate) Supply Chain

SILICON WAFERS (Chapter 3)
    |  300mm wafers for interposer fabrication
    |
    v
INTERPOSER FABRICATION (TSMC, primarily)
    |  Silicon interposer with through-silicon vias (TSVs)
    |  Patterned using DUV lithography
    |
    |---> ABF SUBSTRATE MANUFACTURING
    |    Ajinomoto: ABF film (sole material supplier)
    |    Substrate fabricators: Unimicron, Ibiden, AT&S,
    |    Nan Ya PCB, Shinko Electric, Kinsus
    |
    v
CoWoS ASSEMBLY (TSMC packaging fabs)
    |
    |  Step 1: Logic die (GPU/accelerator, 3nm/5nm)
    |  Step 2: HBM memory stacks (SK Hynix, Samsung, Micron)
    |  Step 3: Both placed on silicon interposer
    |  Step 4: Interposer bonded to ABF substrate
    |
    |  Equipment used:
    |  - Besi, ASMPT: die bonding / TCB
    |  - KLA, Camtek: inspection
    |  - Disco: wafer dicing/thinning
    |  - Advantest/Teradyne: testing
    |
    v
FINISHED AI ACCELERATOR PACKAGE
    |  (e.g., NVIDIA B200, AMD MI350, Google TPU)
    |
    v
TO SERVER OEMs (Chapter 18) & DATA CENTERS (Chapter 17)

9.3.2 ABF Substrate Supply Chain

AJINOMOTO GROUP (Japan)
    |  Sole manufacturer of ABF (Ajinomoto Build-up Film)
    |  Resin-based insulating film, originated as MSG byproduct
    |
    v
ABF SUBSTRATE FABRICATORS
    |
    |---> Unimicron (Taiwan) --- ~22% global share
    |---> Ibiden (Japan) --- ~19% share
    |---> AT&S (Austria) --- ~16% share
    |---> Nan Ya PCB (Taiwan) --- ~14% share
    |---> Shinko Electric (Japan, Fujitsu sub.) --- ~12% share
    |---> Kinsus Interconnect (Taiwan)
    |---> Samsung Electro-Mechanics (Korea)
    |---> Kyocera (Japan)
    |
    |---> Emerging Chinese:
    |    Shennan Circuit, Shenzhen FastPrint, Zhen Ding
    |
    v
CUSTOMERS
    |---> Foundries: TSMC (CoWoS, InFO), Intel (EMIB, Foveros)
    |---> OSATs: ASE, Amkor, JCET, SPIL
    |---> IDMs: Samsung, Intel, AMD (direct)
    |
    v
FINAL PACKAGE → SYSTEM INTEGRATION

9.3.3 Advanced Packaging Technologies

                    PACKAGING TECHNOLOGIES
                           |
         +-----------------┼-----------------+
         |                 |                 |
    2D (Traditional)   2.5D (Lateral)   3D (Vertical)
         |                 |                 |
    Wire Bond         +----┼----+        +---┼---+
    Flip Chip         |    |    |        |       |
                   CoWoS  EMIB  FoPLP  SoIC  Foveros
                  (TSMC) (Intel)(TSMC) (TSMC) (Intel)
                      |         |        |       |
                      |    I-Cube4       |    X-Cube
                      |  (Samsung)       |  (Samsung)
                      |         |        |
                  Si Interposer |   Hybrid Bonding
                  + TSVs        |   (Cu-to-Cu)
                      |    Glass/RDL     |
                      |   Interposer     |
                      |                  |
                  ABF Substrate     Wafer-level
                  (required)        stacking

9.4 Key Companies

9.4.1 Advanced Packaging Providers (Foundries & OSATs)

Company	Ticker	Exchange	Approx. Mkt Cap	Role	Key Metric
TSMC	2330 / TSM	TWSE / NYSE	~$2.2T	Dominant CoWoS and SoIC provider; largest advanced packaging operation globally	CoWoS capacity doubling annually through 2026; $44.96B capex plan (Feb 2026) heavily weighted to packaging; NVIDIA ~63% of CoWoS demand ¹²³
ASE Holdings	3711	TWSE	~$73.0B	Largest OSAT globally; VIPack platform for chiplets	Advanced packaging revenue $600M (2024) → $1.6B (2025); advanced products >80% of revenue ¹¹
Amkor Technology	AMKR	NASDAQ	~$18.0B	#2 OSAT; US-based; CoWoS-compatible packaging	FY2025 revenue $6.71B; $7B Arizona facility (CHIPS Act); 2026 capex $2.5-3.0B (~3x prior year) ¹¹
JCET Group	600584	Shanghai SSE	~$8.0B	Major Chinese OSAT; flip chip and wafer-level packaging	Growing advanced packaging share; China’s largest OSAT
Intel (Foundry/Packaging)	INTC	NASDAQ	~$628B	EMIB and Foveros 3D stacking; shipped first 18A products with Foveros (Jan 2026)	EMIB provides CoWoS alternative; Foveros for 3D stacking; significant patent portfolio ⁹¹²
Samsung (Packaging)	005930	KRX	~$1.2T	I-Cube4, X-Cube platforms; HBM packaging; “3.3D” advanced packaging for AI chips	Aiming to quadruple advanced packaging output by 2028; HBM4 with hybrid copper bonding ¹²¹³
Powertech Technology	6239	TWSE	~$5.2B	Memory packaging specialist (DRAM, NAND); HBM packaging	Key memory packaging partner for Micron and others
SPIL (Siliconware Precision)	ASE subsidiary	Private	(Part of ASE)	Advanced flip chip, bumping, fan-out	Major OSAT; part of ASE group since 2018

TSMC’s packaging dominance is the central fact of this chapter. TSMC is not just a foundry; it is the world’s largest provider of advanced packaging through its CoWoS, InFO, and SoIC platforms. The company’s packaging fabs in Zhunan, Chiayi, Taichung, and Tainan represent the single largest concentration of advanced packaging capacity on Earth. New Chiayi facilities are expected to create approximately 3,000 jobs as they enter mass production ³. TSMC approved a record $44.96 billion capex plan in February 2026, heavily weighted toward advanced packaging ¹².

Intel’s EMIB (Embedded Multi-die Interconnect Bridge) offers an alternative to CoWoS that does not require a full silicon interposer, potentially reducing cost and increasing substrate size. Intel shipped its first 18A products using Foveros 3D stacking in January 2026 ¹². EMIB’s rise could break the CoWoS monopoly pattern for mid-range AI ASICs, though CoWoS retains advantages in interconnection density for the highest-end GPUs ⁴.

9.4.2 ABF Substrate Manufacturers

Company	Ticker	Exchange	Approx. Mkt Cap	Role	Key Metric
Unimicron	3037	TWSE	~$40.9B	Largest ABF substrate manufacturer; ~22% global share	Engineers embedded at TSMC packaging center 18 months ahead of tape-out; purchased 30% of Corning glass-substrate pilot (Oct 2025, $180M) ⁵⁶¹⁴
Ibiden	4062	TSE	~$8.0B	#2 ABF substrate maker; ~19% share; halogen-free ABF	47 substrate patents filed in 2025; 60% related to embedded capacitors and hybrid glass-organic cores ¹⁴
AT&S	ATS	Vienna	~$4.0B	European ABF leader; ~16% share; only major non-Asian player	€500M Leoben expansion backed by EU Chips funds; +20,000 FC-BGA panels/month by 2027 ¹⁴
Nan Ya PCB	8046	TWSE	~$17.5B	#4 ABF substrate maker; ~14% share; Formosa Plastics Group subsidiary	Strong supply chain relationships in Taiwan
Shinko Electric Industries	6967	TSE	~$5.0B	#5 ABF substrate maker; ~12% share; Fujitsu subsidiary	New Osaka plant increased output 30% (2024); high-frequency substrates for AI ⁵⁶
Kinsus Interconnect	3189	TWSE	~$7.7B	Taiwan-based ABF substrate and IC substrate maker	Gaining share through high-layer-count substrates
Ajinomoto	2802	TSE	~$15.0B	Sole manufacturer of ABF film (the raw material); diversified food/chemicals	ABF is a small fraction of Ajinomoto’s revenue but is the sole-source material for the entire ABF substrate industry
Samsung Electro-Mechanics (SEMCO)	009150	KRX	~$7.0B	ABF substrates for Samsung ecosystem; ~5% share	Captive supplier for Samsung chipsets and memory

The ABF substrate supply chain has a unique structural feature: a single company (Ajinomoto, a Japanese food and chemicals conglomerate) manufactures the ABF film itself, which is then converted into substrates by a concentrated group of fabricators. The five largest fabricators control 74% of substrate output ⁵⁶. Intel, AMD, and NVIDIA have subsidized approximately 50% of expansion capex at the top four suppliers (Ibiden, Shinko, Unimicron, AT&S) because the supply is too strategically important to leave to market forces ⁷. This subsidy structure creates deep customer lock-in.

Glass substrates as a potential disruptor: Multiple companies are developing glass core substrates as an alternative or complement to organic ABF substrates. Glass offers better dimensional stability, lower warpage, and the potential for larger substrate sizes. Unimicron purchased a 30% share of Corning’s glass-substrate pilot in New York for $180 million (October 2025), with 2nm-compatible samples due Q2 2027 ¹⁴. Intel has been developing glass substrate technology. Absolics (a subsidiary of SKC, South Korea) is building a glass substrate plant in Georgia, US. However, glass substrates are at an early stage and are not expected to displace ABF in high volume before 2028-2030 at the earliest.

Company	Ticker	Exchange	Approx. Mkt Cap	Role	Key Metric
TSMC	2330 / TSM	TWSE / NYSE	~$2.2T	Primary fabricator of silicon interposers for CoWoS	Interposer fabrication uses DUV litho on 300mm wafers; vertically integrated with packaging
Global Unichip Corp (GUC)	3443	TWSE	~$6.0B	TSMC subsidiary; provides ASIC design services and interposer design	Critical design partner for CoWoS-based custom chips
Absolics	Private	Private (SKC sub.)	Private	Glass substrate/interposer pilot; Georgia (US) plant under construction	Potential alternative to silicon interposers; backed by SKC (Korea)

9.4.4 Packaging Equipment (Cross-reference with Chapter 4)

Key equipment vendors for this chapter (detailed profiles in Chapter 4):

Besi (hybrid bonding, die attach), ASMPT (die bonders, wire bonders), Kulicke & Soffa (wire bonding, TCB)
EVG, SUSS MicroTec (wafer bonding)
Disco (dicing, thinning)
Camtek, KLA, Onto Innovation (packaging inspection/metrology)
Advantest, Teradyne (test), Aehr Test Systems (wafer-level burn-in)

9.5 Bottleneck Analysis

CoWoS capacity (EXTREME, currently a binding constraint for AI hardware): TSMC’s CoWoS capacity is among the tightest chokepoints in the AI supply chain as of mid-2026, scored at RPN 144 in the cross-cutting FMEA (Chapter 20). NVIDIA’s GPU output is limited not by wafer availability but by CoWoS packaging capacity ¹²³. NVIDIA management confirmed this directly on the Q4 FY2026 earnings call: “CoWoS assembly capacity is oversubscribed through at least mid-2026” ²⁰. TSMC is the dominant provider; Samsung and Intel offer alternatives (I-Cube, EMIB) but at smaller scale and without the same process maturity. Even with TSMC doubling capacity annually, demand (driven by NVIDIA, AMD, Google, Amazon, Microsoft custom silicon) is projected to continue exceeding supply through at least late 2026. The lead time for a new CoWoS line is 18-24 months from construction start to production ramp. CoWoS adds an estimated $2,000-3,000 in processing cost per GPU module, representing roughly 5-8% of module selling price. This is a moderately expensive bottleneck, but its significance is driven by timeline constraints (capacity limits), not unit cost.

ABF substrates (SEVERE): Five companies hold 74% of production ⁵⁶. Qualification of a new ABF substrate for a leading-edge chip takes 12-18 months. In 2023, global substrate production fell 9% short of demand ¹⁰. The industry is transitioning toward 16+ layer substrates for AI chips, where yields are lower and only the top-tier fabricators can deliver. Chipmakers’ direct subsidies (50% of expansion capex) create customer lock-in that further concentrates supply ⁷.

Ajinomoto ABF film (SEVERE, single-source): Ajinomoto is the sole manufacturer of ABF film globally. ABF film is a low-cost input, representing less than 0.5% of the final chip module cost. But it is non-substitutable. A disruption at Ajinomoto’s production facilities would halt substrate manufacturing worldwide. This is the most extreme single-source dependency in the substrate supply chain.

HBM packaging (HIGH): HBM stacking (currently 8-high for HBM3E, moving to 12-high and 16-high for HBM4) requires precision die thinning, TSV formation, and bonding. SK Hynix leads, with Samsung and Micron also producing. The transition to HBM4 introduces hybrid bonding (replacing solder micro-bumps), which adds equipment and yield challenges (see Chapter 8).

Hybrid bonding at scale (EMERGING SEVERE): Hybrid bonding is transitioning from R&D to early production for logic (TSMC SoIC) and is expected for HBM4 memory (2026-2027). As noted in Chapter 4, Besi leads in hybrid bonding equipment with sub-10nm alignment accuracy. The equipment is expensive ($3-12M per unit, potentially $40M+ for complete clusters) ¹⁵ and yield challenges at scale remain. If hybrid bonding yields disappoint, it could delay HBM4 and next-generation 3D chiplet architectures.

Test capacity for advanced packages (MODERATE-HIGH): Testing multi-die packages is far more complex than testing monolithic chips. Each die in an HBM stack must be tested before and after bonding (known-good-die, or KGD, testing). System-level test (SLT) of the complete package adds another step. Advantest and Teradyne are the primary test equipment providers (see Chapter 4, Section 4.4.6). Test time per package is increasing, creating capacity constraints.

9.5b OSAT Capacity Expansion: Who Builds the Relief?

The report identifies CoWoS as a binding constraint. The question investors need answered is: who is building the relief capacity, and when does it arrive? The answer determines whether the packaging bottleneck eases in H1 2027 or H1 2028.

Amkor Technology (AMKR, NASDAQ, ~$18.0B). FY2025 revenue $6.71B (+6% YoY), with advanced packaging at 82.8% of total sales ($5.56B). Amkor is not building a CoWoS competitor; it partners with TSMC to perform the substrate and assembly portions of TSMC’s CoWoS flow. Amkor’s $7B Arizona advanced packaging campus (groundbreaking October 2025, volume production early 2028, 750,000+ sq ft cleanroom, ~3,000 jobs) is the largest OSAT expansion in US history. Customers include NVIDIA (substrate portion of CoWoS) and Apple (FCBGA for M-series chips). FY2026 guidance: 25% Q1 YoY growth, $2.5-3B capex focused on advanced packaging and US expansion. Amkor’s value proposition is not technological superiority over TSMC but geographic diversification and capacity relief.

ASE Technology (ASX, NYSE, ~$73.0B). FY2025 revenue 645B NTD (~$20.5B ¹⁶), the world’s largest OSAT by revenue. Advanced packaging revenue was ~$1.6B in 2025 (roughly 10% of ATM segment), forecast to reach $3.5B by 2026 ¹⁶, a 119% increase. ASE’s proprietary FOCoS-Bridge (Fan-Out Chip-on-Substrate Bridge) is a direct alternative to silicon interposer-based 2.5D packaging, offering lower cost at the expense of some interconnect density. ASE is the primary packaging partner for AMD’s Instinct GPUs and has long-standing relationships with Qualcomm, Broadcom, and MediaTek. The key question: can FOCoS-Bridge achieve the interconnect density required for next-generation AI accelerators, or does it remain a mid-tier solution? If FOCoS-Bridge qualifies for NVIDIA Rubin or AMD MI450, the CoWoS bottleneck eases materially. If it doesn’t, TSMC retains monopoly pricing power at the leading edge.

JCET Group (~$8.0B). FY2025 revenue RMB 38.87B (record). JCET is the third-largest OSAT globally and the largest in China. Advanced packaging revenue was RMB 27B (record). The export control risk is material: if US restrictions expand to cover advanced packaging services performed for controlled chip designs, JCET could be cut off from leading-edge customers, concentrating even more demand on ASE and Amkor.

The capacity expansion supply chain. Every new advanced packaging line, whether at TSMC, Amkor, or ASE, requires the same equipment: Besi hybrid bonding tools (12-18 month lead times), Disco dicing and grinding systems, ASMPT/K&S die attach, Advantest/Teradyne test systems, and KLA/Camtek inspection. These equipment vendors get paid on every capacity expansion, regardless of which company builds the line. This is the picks-and-shovels layer underneath the packaging picks-and-shovels layer. Equipment lead times, not capital, determine how fast packaging capacity can expand.

9.6 Risks

CoWoS overbuild risk: TSMC is expanding CoWoS capacity aggressively, doubling annually through 2026. If AI capex pulls back (the bear case from Chapter 1), excess packaging capacity could suppress returns on TSMC’s investment and reduce equipment demand from vendors like Besi and ASMPT. The packaging-specific bear case is that efficiency improvements (smaller dies, better packaging yield, alternative architectures) reduce per-chip packaging intensity faster than total chip demand grows.

EMIB and alternatives breaking the CoWoS monopoly: Intel’s EMIB, Samsung’s I-Cube4/X-Cube, and emerging fan-out panel-level packaging (FoPLP) could absorb some demand away from TSMC CoWoS. If EMIB proves cost-effective for mid-tier AI ASICs, the pricing power of CoWoS diminishes. NVIDIA is reportedly testing CoWoP (Chip-on-Wafer-on-Platform), which mounts the interposer directly on a PCB, potentially bypassing the ABF substrate entirely ¹¹. If validated for the Grace Rubin 150 platform (expected late 2026), this could restructure the entire ABF ecosystem.

Glass substrates disrupting ABF: Glass core substrates offer advantages for very large packages (better dimensional stability, lower warpage, CTE match to silicon). Multiple companies are investing (Unimicron/Corning, Intel, Absolics/SKC, Samsung Electro-Mechanics). Intel shipped its first mass-market CPU with glass core (Xeon 6+ “Clearwater Forest”) in January 2026. Absolics is entering yield stabilization, targeting mass production by end of 2026. Samsung targets glass interposers by 2028. TSMC targets mass production 2028-2029. The enabling equipment is LPKF Laser & Electronics (LPK, Frankfurt, ~EUR 600-650M), whose patented LIDE (Laser Induced Deep Etching) technology is currently the only production-proven process for forming through-glass vias (TGVs) in glass substrates. TGVs are the electrical pathways through the glass; without them, glass substrates cannot function. LPKF’s European Patent was upheld October 2024 (no appeal filed). Over 80% of major semiconductor players selected LPKF equipment for glass substrate process validation ¹⁷. If glass substrates scale faster than expected, the ABF substrate bottleneck loosens but a new equipment bottleneck (LPKF) emerges at the glass substrate layer. Timeline: 2027-2029 for meaningful volume, not the previously estimated 2032+.

Geographic concentration: Advanced packaging capacity is overwhelmingly concentrated in Taiwan (TSMC), with secondary capacity in South Korea (Samsung), Malaysia (ASE, Intel), and smaller amounts in the US (Amkor Arizona, Intel). A disruption in Taiwan (geopolitical, natural disaster) would cripple global AI hardware production. This is the same geographic risk identified in Chapter 7 (Foundries) but amplified because packaging capacity is even more concentrated than leading-edge wafer fabrication.

Yield risk at advanced nodes: As HBM stacks grow taller (12-high, 16-high) and hybrid bonding pitches shrink, yield becomes a critical concern. A single defective die in a 16-high stack can render the entire stack unusable if not caught before bonding. Heat flux in 3D-stacked packages exceeds 300 W/cm² in AI/HPC applications, pushing thermal management to its limits ⁹. Thermal-induced failures could limit the practical height of HBM stacks.

First principles check: Does the CoWoS bottleneck make fundamental sense? Yes. Advanced packaging requires clean-room-grade facilities, specialized equipment (bonding, dicing, inspection), and deep process expertise that takes years to develop. TSMC has invested billions and iterates its CoWoS process with each generation. A new entrant cannot simply build a CoWoS line and start producing; the yield learning curve alone takes 12-18 months. The bottleneck reflects genuine physical and engineering complexity, not regulatory barriers.